Microprocessors and other integrated circuits (ICs) often incorporate embedded memory such as static random access memory (SRAM). In certain of such ICs the access speed of such memory is of great importance, such as in a level 1 cache or in graphic processors. Although a six transistor (6-T) SRAM cell is the standard in many memory applications and especially in stand-alone memories, the 6-T cell may not be fast enough for high speed applications. For applications requiring high speed read access, a memory cell having separate read stack(s) such as an eight transistor (8-T) or ten transistor (10-T) SRAM cell is the memory cell of choice. SRAM cells with additional read stacks allow the memory state of the cell to be read without disturbing the state of the cell.
The read stack of an 8-T or 10-T SRAM cell includes a read pull down transistor and a read pass gate transistor coupled in series. The read performance of such a SRAM cell can be further enhanced by enhancing the pull-down capability of the read pull down transistor. Unfortunately, conventional methods for enhancing the pull-down capability of the read pull down transistor each come with a drawback. For example, the pull-down capability can be enhanced by increasing the width of the transistor channel or by decreasing the length of the channel since pull-down capability is proportional to the ratio of channel width to channel length (W/L). Increasing the channel width, however, results in a larger SRAM cell and decreasing the channel length can result in variability from device to device and in increased leakage current. Reducing the threshold voltage (Vt) of the read stack can increase the pull-down capability, but also increases the leakage current of the read stack.
Accordingly, it is desirable to provide integrated circuits having SRAM cells with additional read stacks that overcome the problems of conventional ICs. In addition, it is desirable to provide methods for fabricating integrated circuits having SRAM cells with high read performance and low leakage current read stacks. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.